1. Field of the Invention
The invention relates in general to a structure of a multi-level interconnection and a method of fabricating the same, and more particularly to the structure and the fabrication of a multi-level interconnection without using a barrier layer.
2. Description of the Related Art
The increasing of the integration of the integrated circuited (IC) causes the insufficiency of the chip surface for formation of interconnection. To satisfy the requirement of more wiring lines as the device size is shrinking, a design of multi-level interconnection is needed for IC fabrication. The multi-level interconnection is a three-dimensional wiring line structure. To form a multi-level interconnection structure, the first or lower layer of the metal wiring line is first formed, connecting with the source/drain region of the metal-oxide semiconductor transistor (MOS) on a substrate by a contact plug through a contact hole. The second layer of the metal wiring line is then formed, connecting with the first metal wiring line by a via plug through a plug hole. The metal wiring lines can either be made from metal or any conductive material such as polysilicon. More than two layers of metal wiring lines can be formed if necessary.
Conventionally, there are two ways for fabricating plugs and metal lines. The first method includes two steps of forming a plug and a metal wiring line, respectively. A dielectric layer is first formed above a region desired for being coupled. After forming a opening in the dielectric layer by photolithography, a conductive material is deposited in the opening to accomplish the plug. Then, a metal layer is deposited and patterned to form a metal wiring line, connecting with the plug. Finally, an inter-metal dielectric layer is deposited. The other method utilizes a damascene technique, which accomplishes the plug and the metal wiring line simultaneously.
Referring to FIG. 1, which is a cross-sectional views showing the structure of the plug and the metal wiring line fabricated a conventional damascene technique. On a semiconductor substrate 10, a conductive layer 12 is first formed. Then, a dielectric layer 14 id formed on the conductive layer, using a material such as a dielectric layer with low dielectric coefficient. In the dielectric layer 14, an opening 15 and an opening 13 are formed successively. Next, a glue layer 16 is formed on the opening 15 and the opening 13. Generally, the common material for the glue layer 16 includes titanium/titanium nitride (Ti/TiN), tungsten nitride (WN), tantulum or tantulum nitride (TaN). The glue layer 16 is used to enhance the adhesive force of the later deposited conductive material and obstruct the diffusion of the conductive material. Then, a conductive layer 18, such as conductive materials of superior conductivity, tungsten or aluminum. Then, a chemical mechanical polishing (CMP) is performed to accomplish the conventional damascene process.
However, as the size of semiconductor devices keeps on shrinking, the width of the via hole or the contact hole is desired to be narrower and the aspect ratio becomes much higher than before. Conventionally, before filling of the conductive material, a glue layer is formed on the inner periphery of the hole so that the width of the hole will reduce. If the step coverage of the conductive material is poor, which is usually in this case and difficult to overcome, short circuit tends to occur and the difficulties in filling conductive layer into the hole becomes even greater.